In data processing systems, which comprise a plurality of processors or processing units, i.e. in multi-processor systems, each processor or processing unit can be adapted to process or execute a task. These tasks may also include tasks, which need to be processed in real-time as these tasks have strict deadlines associated to their processing. In such data processing systems, interrupts may occur which have to be processed by one of the processors. To be able to process the interrupt, the currently processed task is stopped or interrupted. For example, if the processor is performing some real-time tasks and if this processing is interrupted, the processing of the real-time tasks may not meet the real-time requirements. This could lead to an increase in the scheduling latency, which should be avoided in some multimedia applications.
In particular, if a plurality of processors is present in a data processing system, typically not all of the processors will be performing real-time tasks such that the interrupts may be handled by a further processor.
US 2003/0105798 A1 relates to an interrupt distribution scheme based on interrupt characteristics such as the priority of a device or an interface, the priority of a thread or an application which are running on different processors.
US 2002/0166018 relates to a dynamic routing and priority assignment of an interrupt. The interrupt controller is dynamically controlled by programming at least one register.
U.S. Pat. No. 6,877,057 B2 teaches a scheme of a uniform distribution of interrupts across units on a processor circuit board and devices on any extension slots.
US 2003/0200250 A1 concerns a dynamic reassignment of interrupt service routines ISR to processors based on the run-time statistics like the execution times of the interrupt service routines.
However, in the interrupt distribution according to the prior art, no information with respect to the tasks is included which is awaiting processor times and information with respect to the state of the execution of a process on a processor during the interrupt handling and distribution.